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Books & Guides    Language         Tools & Utilities    Models


Books & Guides

bulletBooks (Search for Verilog)
bulletAll IEEE standards can be obtained from http://www.ieee.org
bulletOn-line Verilog quick reference guide
bulletAlternate Verilog FAQ
bulletHot PLI Stuff
bulletUsenet groups: comp.lang.verilog, comp.lang.synthesis
bulletCelia's Verilog & EDA Web page
bulletQuick Reference Cards: Comit, Qualis
bulletFree stuff
bulletUnderstanding CRCs
bulletSynthesis and scripting techniques for designing multi-asynchronous clock designs
bulletPeter Chambers "10 commandments of excellent design"  
bulletPublic domain verilog resources
bulletPLI info
bulletVerilog HDL Coding Style Guide
bulletThe HDL Page (EDAI)
bullet"Moving Data Across Asynchronous Clock Boundaries" by Peter Alfke
bulletAlternate Verilog FAQ
bulletRajesh Bawankule's Verilog Center
bulletCSCI 320 Computer Architecture Verilog Manual
bulletVerilog.Net - Premiere List of Verilog Resources on the Internet
bulletCelia's Verilog & EDA Web Page
bulletVerilog HDL
bulletHome of Verilog Quickstart
bulletOpen Directory - Computers: Programming: Languages: Verilog
bulletFAQ: Comp.lang.verilog Frequently Asked Questions (with answers)
bulletVerilog-mode : SureFire
bulletVerilog(TM) HDL LRM project : M. Smith
bulletBucknell Verilog Manual
bulletA Brief Introduction to PLI (Programming Language Interface)
bulletJimen Ching's Web Page
bulletAMIS | Verilog
bulletEE271/272 Verilog FAQ : Stanford
bulletSilicon Sorcery
bulletTek-Tips Forums for computer professionals
bulletverilog - best of the web - hdl
bulletHDL, VHDL, Verilog and FPGA Training from Esperan
bulletFPGA, VHDL, Verilog Newsgroups
bulletComit Systems - Free Downloads
bulletRiviera Verilog PLI Interface
bulletECE347 Verilog Resources : CMU
bulletverilog - internet resources (verilog)
bulletASIC laboratory Heidelberg
bulletVerilog Computer-Based Training Course CD-ROM
bulletVerilog : UA
bulletQualis Course: Jump Start for Verilog Verification
bulletVerilog Links
bulletVerilog Information : UI
bulletUsing Verilog
bulletMixed-Signal Modeling with Vanilla VHDL and Verilog
bulletMultisim Education Verilog
bulletComprehensive Verilog Design 4 days : TM Associates
bulletEWB Multisim VHDL/Verilog Design/Simulation
bulletVerilog  : NEU
bulletEKV v2.6 Verilog-A implementation
bulletVerilog Exercises
bulletVerilog Models
bulletVerilog Tutorial Frame 6
bulletIntro to Verilog v5 : Xilinx
bulletcomp.lang.verilog Newsgroup FAQs
bulletASPN : Modules
bulletEWB Multisim Verilog
bulletVerilog-A Release in SmartSpice
bulletVerilog Resources
bulletRajesh Bawankule's Verilog Center: Free Stuff
bulletCSCI Computer Architecture Verilog Manual
bulletProgrammer's Oasis - Verilog
bulletHDL Planet's Verilog Page
bulletECE 475 Verilog Manual : CU
bulletAbstract State Machines: VHDL and Verilog


bulletVerilog HDL Working Group : Group in charge of Verilog HDL, IEEE Std 1364
bulletVerilog Synthesis Interoperability Working Group: Group in charge of development of RTL standard IEEE Std 1364.1
bulletVerilog 2000: What's new
bulletVerilog tutorial
bulletVerilog-93 syntax
bulletOnline Verilog tutorial
bulletTutorial on Verilog
bulletVerilog Quick Reference Card
bulletVerilog Tutorials (OptiMagic)
bulletIntroduction to Verilog
bulletVerilog HDL On-line Quick Reference, by Sutherland HDL, Inc., ...
bulletVerilog-AMS Home
bulletVerilog-2001 Information Page by Sutherland HDL, Inc.
bulletVHDL and Verilog References and Tutorials : Optimagic
bulletVerilog tutorials for beginners : 1001 Tutorials
bulletDesigner's Guide to Verilog : Doulos
bulletLearn Verilog On-line
bulletVerilog tutorials online!
bulletAn Introduction to Verilog
bulletVerilog HDL On-line Quick Reference body
bulletCSCI 320 Computer Architecture Handbook on Verilog HDL
bulletVerilog HDL Coding Style Guide
bulletVerilog Style Manual
bulletVerilog Quick Ref Card
bulletVerilog-XL Reference -- Table Of Contents


Tools & Utilities

bulletFree Verilog Simulator: LogicSim
bulletVerilog for emacs and Xemacs
bullethdlmaker: Generating top-level netlist from lower-level blocks
bulletmktree: Creating module connection files
bulletFree Verilog simulator: Icarus Verilog
bulletVerilator: Free Verilog to C++ simulator
bulletC-like file I/O
bulletVerilog HDL Obfuscator
bulletFree Verilog Simulator, Windows 98: SILOS III
bulletSource Navigator
bulletPerl/Python/Tcl Interface to VPI
bulletFree Viewer
bulletInstance name extraction
bulletFree timing diagram editor
bulletFree Verilog PC simulator: cygwin
bulletConnect modules (Topweaver)
bulletInteractive Design and Simulation System (IDaSS)
bulletSFL to Verilog
bulletIcarus Verilog
bulletMac's Emacs Mode
bulletv2html - verilog to html converter
bulletVerilog HDL Simulators - EDA Tools for FPGA and ASIC Digital ...
bulletSource Navigator for Verilog
bulletFreeware EDA Tools Page
bulletAldec - Free Downloads
bulletVer Structural Verilog Compiler
bulletFree Verilog HDL Simulator - Silos Free Demo Software
bulletVerilog-Perl : Wilson Synder
bulletVerilog Formal Equivalence Project
bulletVerilog++: a Verilog preprocessor
bulletv2html - Rough Verilog Parser
bulletVerilog Tag2 Script
bulletVerilog PreProcessors
bulletVTM - Verilog Template Maker
bulletScriptSim Verilog PLI Perl/Python/Tk Interface Introduction
bulletverilog2vhdl (tm) Verilog to VHDL translation
bulletVerilog Model Generators: VeriGen and VeriTest
bulletFile I/O for Verilog models
bulletNetman: Verilog Netlist manager/viewer
bulletInst Verilog Generation Functions
bulletPerlilog: IP integration Tool



bulletSynthesizable microprocessor
bulletRTL descriptions of Flip-flops
bullet16bit risc cpu core
bulletUtopia 4
bulletUART design, also here, and here
bulletEthernet (802.3) MAC model
bulletFlash Memory
bulletI2C Slave Interface
bullet8x8 DCT, fully pipelines
bulletQNR, Quantization & Rounding unit
bulletRun-Length encoder
bulletHuffman Encoder
bulletHuffman Decoder
bulletHardware Dividers
bulletTriple DES
bulletUSB 1.1 Phy
bulletAsynchronous Serial IO Controller
bulletSingle Slot PCM Controller
bulletUSB 1.1 Function IP Core
bulletGeneric FIFOs
bulletCPU/Microcontroller (PIC Clone) IP Core
bulletDES IP Core
bulletSingle Precision FPU (IEEE-754 compliant) IP Core
bulletUSB 2.0 Function (Slave) IP Core
bulletDMA/Bridge IP Core
bulletAdvanced Memory Controller IP Core
bulletAC97 Controller IP Core
bulletWISHBONE Interconnect Matrix
bulletSSRAM Interface
bulletATA/ATAPI Host Controller
bulletI2C Master Controller
bulletVGA/LCD Controller
bulletCORDIC Core
bulletVideo Compression System
bulletOpen 54x DSP clone
bulletPCI Model
bulletVerilog HDL Examples : Altera
bulletCMOSexod.com your source of free Verilog/VHDL IPs.
bulletVERILOG description : UCB
bulletVHDL/Verilog Models : Denali
bulletVerilog,HDL,bus interface,core logic,bus architecture,IP blocks, ...
bulletFree RISC8 (Verilog)
bulletThe RISC8 Verilog core
bulletDCD - Digital Core Design - VHDL and Verilog IP Cores supplier



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Star Galaxy Publishing <webmaster@stargalaxypub.com
Last updated: January 12, 2003