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Star Galaxy Publishing

 


"They call me Bond .... James Bond!"

[Photo:J.Bhasker]

J. Bhasker
eSilicon Corporation
1605 N Cedar Crest Blvd, Suite 615
Allentown, PA 18104
610.439.6831
jbhasker@esilicon.com

Now you can hear his voice every third Saturday of the month from 8:00am to 10:00 am EST on WMUH 91.7FM, Allentown, PA hosting the "Music of India" program.

J.Bhasker (he is called by his last name "Bhasker" and as "Bond" by his more intimate friends) has been involved with VHDL, Verilog HDL, and synthesis for more than ten years and he is one of the main architects of the ArchSyn synthesis system. He has coached a number of colleagues at AT&T/Lucent through classes on VHDL, Verilog HDL and synthesis.

Books Published

bulletA SystemC Primer, Second Edition, 2004, Star Galaxy Publishing.
bulletVerilog HDL Synthesis, A Practical Primer, Chinese Edition, 2004, Tsinghua University Press.
bulletA SystemC Primer, 2002, Star Galaxy Publishing.
bulletChapter on "Synthesis at the Register Transfer Level and Behavioral Level" in book "Circuits and Filters Handbook", 2002, CRC Press.
bulletChapter on "VHDL-2000: What's New" with Paul Menchini in book "The Best of FDL & HDL 2001", 2002, Kluwer Academic Publishing.
bulletA VHDL Synthesis Primer, Second Edition, Indian Edition, 2001, BS Publications.
bulletA Verilog HDL Primer, Second Edition, Indian Edition, 2001, BS Publications.
bulletVerilog HDL Synthesis, A Practical Primer, Indian Edition, 2001, BS Publications.
bulletVerilog HDL Synthesis, A Practical Primer, Japanese Edition, 2001, CQ Publishing.
bulletA Verilog HDL Primer, Second Edition, Chinese Edition, 2000, China Machine Press.
bulletChapter on "Synthesis at the Register Transfer Level and the Behavioral Level" in book "A VLSI Handbook", 2000, CRC Press.
bulletA Verilog HDL Primer, Second Edition, 1999, Star Galaxy Publishing.
bulletA VHDL Primer, Third Edition, 1999, Prentice Hall.
bulletVerilog HDL Synthesis, A Practical Primer, 1998, Star Galaxy Publishing.
bulletA VHDL Synthesis Primer, Second Edition, 1998, Star Galaxy Publishing.
bulletA Verilog HDL Primer, 1997, Star Galaxy Press.
bulletA VHDL Synthesis Primer, 1996, Star Galaxy Publishing.
bulletVHDL Features and Applications: A self-study guide, 1996, IEEE.
bulletDie VHDL-Syntax, German Edition, 1996, Prentice Hall.
bulletA VHDL Primer: Revised Edition, 1995, Prentice Hall.
bulletA VHDL Primer, Japanese Edition, 1995, CQ Publishing.
bulletA Guide to VHDL Syntax, 1995, Prentice Hall.
bulletA VHDL Primer, 1992, Prentice Hall.

Education

bulletPh.D., Computer and Information Sciences - University of Minnesota, Minneapolis, Minnesota, 1985, C. G. P. A. = 4.00/4.00.
bulletM. Tech., Computer Technology - Indian Institute of Technology, New Delhi, India, 1982, C. G. P. A. = 9.89/10.00.
bulletB. Tech., Electrical Engineering - Indian Institute of Technology, New Delhi, India, 1977, first division with distinction.

Professional Activities

bulletChair, IEEE Std 1076.6 VHDL Synthesis Interoperability Working Group, 1996-.
bulletChair, IEEE Std 1364.1 Verilog Synthesis Interoperability Working Group, 1998-.
bulletProgram Committee member, Forum for Design Languages, FDL'98.
bulletProceedings Chair, VHDL International Users Forum, Fall 1997.
bulletTechnical Program Chair, VHDL International Users Forum, Fall 1995.
bulletProgram Committee member and session chair, VHDL International Users Forum, Fall '93, Spring '94, Fall '94, Spring '95, Fall '95, Spring '96, Fall '96, Spr '97, Fall '97, Fall '99.
bulletProgram Committee member, EuroVHDL, 1996-97.
bulletProgram Committee member, APCHDL, 1996-97.
bulletChair, VHDL-EDIF Interoperability Working Group - PAR 1165, IEEE DASC, 1993-94.
bulletBallot Chair, VHDL Synthesis Working Group - PAR 1076.3, IEEE DASC, 1994.
bulletMember, VHDL Analysis and Standardization Committee, DASC Steering Committee, IEEE DASC, 1993-94.
bulletHoneywell Excel Pioneer Award, 1987.
bulletReferee, International Conference on Parallel Processing 1987, IEEE/ACM Design Automation Conference 1986 - 1987, 1999, Journal of Parallel and Distributed Computing 1987, EuroDAC 1993-94.
bulletPhi Kappa Phi member, 1985.
bulletMEIS Fellow, 1982-1984.

Tutorial Presentations

bulletThe Two IEEE Standards for VHDL RTL Synthesis: Making Your Designs Portable, FDL 2001, Lyon, France.
bulletAn Introduction to Verilog HDL Synthesis, HDL Conference, Santa Clara, CA Spring 1999.
bulletHigh Performance RTL Coding Styles for Synthesis with Joe Pick and Egbert Molenkamp, 35th Design Automation Conference, San Francisco, 1998.
bulletVHDL Synthesis: An Introduction, VIUF Conference, Santa Clara, CA, Spring 97.
bulletVHDL Synthesis: A Practical Primer, APCHDL'97 Conference, Hsinchu, Taiwan, 1997.
bulletThe IEEE Standard VHDL Synthesis Packages: IEEE Std 1076.3-1996 with Jim Vellenga, VIUF Conference, Durham, N. Carolina, Fall 1996.
bulletIEEE Standard 1076.3-1996 VHDL Synthesis Packages ASIC Conference, Rochester, NY, 1996.
bulletAn Early Bird Look at the 1076.3 VHDL Synthesis Packages with Jim Vellenga, VIUF Conference, San Diego, CA, Spring 1995.

Journal Publications

bulletQuest for VHDL Synthesis Solutions, VI Times, Article Series, 1996-1998.
bulletDatapath Synthesis using a Problem Space Genetic Algorithm with M.K. Dhodhi, F. Hielscher and R. Storer, IEEE Transactions on CAD for ICs and Systems, Vol 14, No 8, pp934-944, Aug 1995.
bulletSize, Chromatic Number, and Connectivity with Douglas West and Tariq Samad, Graphs and Combinatorics, 1994.
bulletThe Clique-Partitioning Problem with Tariq Samad, Computers Mathematics and Applications, Vol 22, No 6, pp1-11, 1991.
bulletWriting Verilog HDL models for synthesis: A user's guide, AT&T Bell Labs Technical Memorandum, April 1991.
bulletSATYA: A Simulation-based Test System for High-level Synthesis Verification with Rolf Ernst, IEEE Design and Test, Vol 8, No 1, pp14-20, March 1991.
bulletSimulating VHDL behavioral models: A user's guide, AT&T Bell Labs Technical Memorandum, July 1990.
bulletAn Optimizer for Hardware Synthesis with Huan-Chih Lee, IEEE Design and Test, 1990.
bulletddb2vhdl: Translating structural descriptions in DDB to VHDL with S.R. Easwar and S. Rothweiler, AT&T Bell Labs Technical Memorandum, Feb 1990.
bulletModeling in VHDL for BESTMAP synthesis, AT&T Bell Labs Technical Memorandum, Dec 1989.
bulletPerformance Improvement Techniques for Synthesis with Rolf Ernst and Chia-Jeng Tseng, AT&T Bell Labs Technical Memorandum, 1989.
bulletVia Assignment in Single Row Routing with S. Sahni, IEEE Transactions on Computers, Vol 38, No 1, Jan 1989, pp142-148.
bulletScheduling in BRIDGE, AT&T Bell Labs Technical Memorandum, Dec 1988.
bulletA Better Clique-Partitioning Algorithm with Tariq Samad, Proc. Allerton Conference on Communication, Control and Computing, Sept. 1988, pp808-809.
bulletProcess-Graph Analyzer: A Front-End Tool for VHDL Behavioral Synthesis, Software Practice & Experience, Vol 18, No 5, May 1988, pp469-484.
bulletImplementation of an Optimizing Compiler for VHDL, SIGPLAN Notices, Jan 1988.
bulletA Linear Algorithm to Find a Rectangular Dual of a Planar Triangulated Graph with S. Sahni, Algorithmica, Springer-Verlag, 1988, 3, pp247-278.
bulletAn Algorithm for Microcode Compaction of VHDL Behavioral Descriptions, IEEE VLSI Technical Bulletin, Vol 2, No 2, June 1987.
bulletA Linear Algorithm to Check for the Existence of a Rectangular Dual of a Planar Triangulated Graph with S. Sahni, Networks, Vol 17, 1987, pp307-317.
bulletOptimal Linear Arrangement of Circuit Components, with S. Sahni, Journal of VLSI and Computer Systems, Vol 2, No 1&2, 1987, pp87-109.
bulletA Linear Algorithm to Check for the Existence of a Rectangular Dual of a Planar Triangulated Graph, with S. Sahni, Proceedings of the 20th Hawaii International Conference on System Sciences, 1987, pp.31-38.
bulletOptimal Linear Arrangement of Circuit Components, with S. Sahni, Proceedings of the 20th Hawaii International Conference on System Sciences, 1987, pp. 99-111.
bulletAn Optimizer for Hardware Synthesis, Scientific Honeyweller, Vol 7, No 3, Winter 86-87, pp. 23-34.
bulletVia Assignment in Single Row Routing, with S. Sahni, Foundations of Software Technology and Theoretical Computer Science, Springer Verlag, Lecture Notes in Computer Science #241, 1986, pp 154-176.

Conference Publications

bulletFunctional Coverage Analysis in the Verification Cockpit with Tom Fitzpatrick, Erich Marschner, Cadence Technical Conference, San Diego, CA, 2001.
bulletVHDL-2000: What's New with Paul Menchini, Best Paper Award, International HDL Conference, Santa Clara, CA, 2001.
bulletA Standard for Verilog HDL RTL Synthesis, HDL Conference, Santa Clara, April 1999.
bulletSynthesis Interoperability and its Impact on Code Reusability, Invited Talk, VHDL User's Forum in Europe '97, Toledo, Spain, April 1997.
bulletVerilog netlist as an exchange language with Jen-Jen Lung, International Verilog HDL Conference, pp10-14, 1994.
bulletExploring the Design Space in High-level Synthesis with Mike Tong, IEEE CICC, pp 29.2.1-29.2.4, May 1990.
bulletSynthesis of Behavioral Descriptions into ASIC Architectures, with Huan-Chih Lee, International Workshop on High-Level Synthesis, January 1988.
bulletVHDL as a Synthesis Language, IEEE Design Automation Workshop, January 1988.
bulletProcess Graph Analyzer: A Front End Tool for VHDL Behavioral Synthesis, Proceedings of the 21st Hawaii International Conference on System Sciences, Vol 1, Jan 1988, pp248-255.
bulletAn Algorithm for Microcode Compaction of VHDL Behavioral Descriptions, Proceedings of the 20th Microprogramming Workshop, Dec 1987.
bulletCompacting MIMOLA Microcode with Tariq Samad, Proceedings of the 20th Microprogramming Workshop, Dec 1987.
bulletV-Synth: A VHDL Behavioral Synthesis System with S. Krolikoski and S. Natarajan, International Workshop on Logic Synthesis, Research Triangle Park, North Carolina, May, 1987.
bulletThe V-Synth System, with S. Krolikoski, and S. Natarajan, Honeywell CAD/CAM Technology Update, 1986.
bulletA Linear Algorithm to Find the Rectangular Dual of a Planar Triangulated Graph, with S. Sahni, 23rd ACM/IEEE Design Automation Conference Proceedings, 1986.
bulletProcess Graph Analyzer, Honeywell Computer Sciences Forum, Vol 10, #3, October, 1986, pp. 27-32.
bulletProcess Graph Analyzer, 10th Annual Honeywell International Computer Sciences Conference Proceedings, 1986.

Work History

bulletOctober 1998 - present: Senior Architect, Cadence Design Systems.
bulletMarch 1988 - September 1998: Distinguished Member of Technical Staff, Bell Laboratories, Lucent Technologies.
bulletJuly 1988 - 1992: Adjunct Faculty, Dept. of Computer Science and Elect. Eng., Lehigh University, Bethlehem.
bulletOctober 1985 - Febraury 1988: Principal Research Engineer, Honeywell Corporate Systems Development Division, Golden Valley, Minnesota.
bulletOctober 1985 - Febraury 1988: Adjunct faculty, Department of Computer Science, University of Minnesota, Minneapolis, Minnesota.
bulletSeptember 1982 - October 1985: Teaching assistant/Research assistant, Department of Computer Science, University of Minnesota, Minneapolis.
bulletJune 1983 - December 1984: Student programmer, CAD department, Sperry Computer Systems, Roseville, Minnesota.
bulletSeptember 1981 - July 1982: Senior Design Engineer, Applied Electromagnetics, New Delhi, India.
bulletJune 1977 - August 1981: Design and Development Engineer, Continental Device, New Delhi, India.
 

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Last updated: January 12, 2003