SystemVerilog primer book

A SystemVerilog Primer


Primer based on IEEE Std 1800-2009.

Table of Contents
Hardcover, 320 pages
US$99.95 (Quantity discounts)
ISBN 978-0-9650391-1-6
Star Galaxy Publishing, 2010

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"A must primer for anyone who is beginning to learn SystemVerilog"

"An excellent reference book that shows many modeling examples"

Learn SystemVerilog the fast and easy way. Use this primer for a thorough understanding of the basic building blocks of SystemVerilog.
Find out how to model hardware and test it using the various constructs provided by SystemVerilog.

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Reader comments:

" It is an awesome book - on the same lines as your other texts. It is a very good companion to the Verilog Primer and brings out the most important concepts of the SV language with easy to understand examples. " 
- Preetham Lakshmikanthan, Intel

" A SystemVerilog Primer is an excellent resource to get up to speed on the application of the various features of SystemVerilog per IEEE 1800-2009. The explanations of each feature is provided with examples and guidelines, where appropriate." 
- Ben Cohen, Author/Consultant, http://SystemVerilog.us

" This is a nice book, well organized and full of concrete examples that illustrates well on how to use SystemVerilog. Readers will appreciate the simple descriptions for the complex language features. " 
- Francoise Martinolle, Cadence Design Systems

" The book is very useful for someone who just wants to know what the practical elements of the language are and as a quick reference book." 
- Ambar Sarkar, Paradigm Works

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