SystemVerilog primer book
A SystemVerilog Primer
Primer based on IEEE Std 1800-2009.
Table of Contents
Or you can order it through your favorite
Hardcover, 320 pages
US$99.95 (Quantity discounts)
Star Galaxy Publishing, 2010
"A must primer for anyone who is beginning to learn
"An excellent reference book that shows many modeling
|Learn SystemVerilog the fast and easy way. Use this primer for a thorough
understanding of the basic building blocks of SystemVerilog.|
|Find out how to model hardware and test it using the various constructs
provided by SystemVerilog.|
- Written for new users
- Explains the language through simple examples
- Explains the syntax of language using commonly-used design terminology
- Writing is made easier by providing a number of examples
- Many hardware modeling examples also been provided to make this an excellent reference
" It is an awesome book - on the same lines as your other texts. It is a very good companion to
the Verilog Primer and brings out the most important concepts of the SV language with easy to understand examples. "
- Preetham Lakshmikanthan, Intel
" A SystemVerilog Primer is an excellent resource to get up to speed
on the application of the various features of SystemVerilog per IEEE 1800-2009.
The explanations of each feature is provided with examples and guidelines, where appropriate."
- Ben Cohen, Author/Consultant, http://SystemVerilog.us
" This is a nice book, well organized and full of concrete examples that illustrates well on how to use SystemVerilog.
Readers will appreciate the simple descriptions for the complex language features. "
- Francoise Martinolle, Cadence Design Systems
" The book is very useful for someone who just wants to know what the practical
elements of the language are and as a quick reference book."
- Ambar Sarkar, Paradigm Works
You are visitor number Thanks for visiting!