VHDL synthesis Primer

A VHDL Synthesis Primer

Table Of Contents

[Front cover]Second Edition
312 pages
 US$84.95(Quantity discounts)
ISBN 0-9650391-9-6
Star Galaxy Publishing
August, 1998


Or you can order it through your favorite bookstore.

Learn to Model for Synthesis using VHDL!

This book is a must primer for anyone who is beginning to learn synthesis using VHDL. A chapter on verification explains the many causes of simulation mismatches between pre and post synthesis models and on how to avoid these. Modeling guidelines are also provided to help improve synthesis results.

Reader comments:

"Thank you for sending me your excellent books to take a look at. I was so impressed that next semester we are going to make your Synthesis primer required text for our VHDL 2 course. Thanks again for writing such excellent and practical material." 
- Prof. Fouad Kiamilev(*), University of North Carolina

"I've learned about the subset of VHDL that a synthesis tool that we use synthesizes by trial and error over a year and a half, and this book would have saved me a lot of time" 
- Andy Fingerhut, Washington University

"The book gives a good impression what is, and is not synthesizable. Furthermore the influence of a VHDL description on the synthesis results is written in a clear way" 
- Egbert Molenkamp, University of Twente, The Netherlands

"I don't think I have seen anyone cover VHDL synthesis in a general way as well as you have. I certainly think this will be a successful book" 
- Rich Hatcher, Texas Instruments

"This (Bhasker's latest) book on VHDL Synthesis should be on the "Best Sellers List" in our mind. It's a well written text with plenty of examples to get you started in the right direction" 
- William Billowitch, The VHDL Technology Group

"It (book) is well written and practical" 
- Milan Gandhi, Indus Consulting

"It (book) is an excellent treatment of VHDL synthesis and was quite helpful in understanding simulation/synthesis mismatches" 
- Victor Berman, DASC Chair

" This book is easy to read with many small examples. With it, you can quickly learn how synthesizers produce the circuits from the VHDL descriptions" 
- Prof. Jing-Yang Jou, National Chiao Tung University

"It (book) is very clear and concise; it is a good book and highly recommended" 
- Doug Smith, VeriBest

" It has the level of technical detail that is missing in so many books and I am seriously considering the book as a textbook" 
- Prof. Stu Tewksbury(*), Stevens Institute of Technology

"This is really well written -clear, comprehensive, with lots of examples. So, I will recommend it for my students for the second part of semester this fall" 
- Prof. Otto Fucik(*), University of Wyoming

"I use the book as a reference to see what kind of VHDL generates what logic. For example, if I want to see how "for" loops are handled, i go directly to the section where an example shows me how to model for synthesis and what kind of gates are produced. It is THE reference guide for me in my designs ..." 
- Mourad Takla, IC designer, Lucent Technologies

"Overall, it looks like a good level for an introductory course in VHDL-based synthesis" 
- Jim Vellenga, ViewLogic Systems

"I have a copy of your book and like it very much. " 
- Prof. Frank Scarpino (*), University of Dayton

"I just bought your book "A VHDL SYNTHESIS PRIMER" and I enjoy it very much" 
- Iuval Jaschevatzky (*)

"We live for your book! NO JOKE" 
- Rick Eesley (*), Bell Labs


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