A VHDL Synthesis Primer, Second Edition: Table of contents

A VHDL Synthesis Primer, Second Edition: Table of contents

Chapter 1
Language Basics	1
	1.1.	About VHDL,  1
	1.2.	Design Units,  2
	1.3.	Data Objects,  4
	1.4.	Data Types,  5
	1.5.	Design Description,  6
	1.6.	Design Libraries,  10
	1.7.	Simulating a Model,  10
	1.8.	Synthesizing a Model,  11
Chapter 2
Synthesis Basics	12
	2.1.	What is Synthesis?,  13
	2.2.	Synthesis in a Design Process,  14
	2.3.	Value Holders for Hardware Modeling,  16
	2.4.	Logic Value System,  20
	2.5.	Computing Bit-widths,  20
	2.5.1.	Integer Types,  21
	2.5.2.	Type BIT_VECTOR,  22
	2.5.3.	Enumeration Types,  23
	2.5.4.	Encoding Metalogical Values,  25
	2.5.5.	Array Types,  28
	2.5.6.	Signed and Unsigned Types,  28
	2.6.	1076.3 Arithmetic Packages,  30
	2.7.	Resolution Functions,  32
Chapter 3
Mapping Statements to Gates	34
	3.1.	Assignment Statement,  35
	3.2.	Logical Operators,  37
	3.3.	Arithmetic Operators,  39
	3.3.1.	Unsigned Arithmetic,  39
	3.3.2.	Signed Arithmetic,  40
	3.3.3.	Computing Result Size,  42
	3.3.4.	Modeling a Carry,  43
	3.4.	Relational Operators,  43
	3.5.	Vectors and Slices,  45
	3.5.1.	Constant Index,  46
	3.5.2.	Non-constant Index,  46
	3.6.	Process Statement,  49
	3.7.	If Statement,  51
	3.7.1.	Inferring Latches from If Statements,  54
	3.8.	Case Statement,  58
	3.8.1.	Inferring Latches from Case Statements,  61
	3.9.	Loop Statement,  63
	3.10.	Null Statement,  64
	3.11.	Wait Statement,  65
	3.12.	Modeling Flip-flops,  71
	3.12.1.	Multiple Clocks,  75
	3.12.2.	Multi-phase Clocks,  76
	3.12.3.	With Asynchronous Preset and Clear,  77
	3.12.4.	With Synchronous Preset and Clear,  81
	3.13.	Modeling Latches,  83
	3.14.	Other Forms of Signal Assignment,  85
	3.14.1.	Conditional Signal Assignment Statement,  85
	3.14.2.	Selected Signal Assignment Statement,  86
	3.14.3.	Sequential Signal Assignment Statement,  87
	3.15.	Functions,  89
	3.16.	Procedures,  91
	3.17.	Records,  94
	3.18.	Block Statement,  96
	3.19.	Using Metalogical Values,  96
	3.19.1.	The Don't-care Value (D),  98
	3.19.2.	The Unknown Value (U),  100
	3.19.3.	The High-impedance Value (Z),  100
	3.19.4.	Wild Card Matching,  102
	3.20.	Component Instantiation Statement,  103
	3.21.	Using Predefined Blocks,  104
	3.22.	Generics,  107
	3.23.	Generate Statement,  108
Chapter 4
Model Optimizations	111
	4.1.	Resource Allocation,  112
	4.2.	Conversion Functions,  115
	4.3.	Type INTEGER,  116
	4.4.	Common Subexpressions,  117
	4.5.	Moving Code,  118
	4.6.	Common Factoring,  119
	4.7.	Commutativity and Associativity,  120
	4.8.	Other Optimizations,  121
	4.9.	Flip-flop and Latch Optimizations,  121
	4.9.1.	Avoiding Flip-flops,  121
	4.9.2.	Avoiding Latches,  123
	4.10.	Design Size,  124
	4.11.	Using Parenthesis,  125
	4.12.	Building with Predefined Blocks,  127
	4.13.	Using One Adder,  128

Chapter 5
Verification	130
	5.1.	Entity Interface,  131
	5.2.	A Test Bench,  132
	5.3.	Delays in Assignment Statements,  136
	5.4.	Unconnected Ports,  137
	5.5.	Signals vs. Variables,  139
	5.6.	Variables and Latches,  141
	5.7.	Inertial and Transport Delays,  143
	5.8.	Resolution Function,  144
	5.9.	Built-in Types and Functions,  145
	5.10.	Sensitivity List,  146
	5.11.	Initialization,  147
	5.12.	Using Attribute ENUM_ENCODING,  152
Chapter 6
Modeling Hardware Elements for Synthesis	154
	6.1.	Modeling a Wire,  155
	6.2.	Modeling Combinational Logic,  157
	6.3.	Modeling Sequential Logic,  158
	6.4.	Modeling a Flip-flop,  159
	6.4.1.	From a Signal,  160
	6.4.2.	From a Variable,  161
	6.5.	Flip-flop with Asynchronous Preset and Clear,  162
	6.6.	Flip-flop with Synchronous Preset and Clear,  164
	6.7.	Modeling a Latch,  167
	6.8.	Latch with Asynchronous Preset and Clear,  169
	6.9.	Modeling a Memory,  171
	6.10.	Using a Pre-built Component,  173
	6.11.	Writing Boolean Equations,  174
	6.12.	Modeling a Finite State Machine,  176
	6.12.1.	Moore FSM,  176
	6.12.2.	Mealy FSM,  180
	6.12.3.	Encoding States,  185
	6.12.4.	Another Example,  188
	6.13.	Modeling an Universal Shift Register,  191
	6.14.	A Generic Parallel to Serial Converter,  193
	6.15.	Modeling an ALU,  194
	6.15.1.	A Generic ALU,  194
	6.15.2.	A Simple ALU,  197
	6.16.	Modeling a Counter,  198
	6.16.1.	Ripple Counter,  198
	6.16.2.	Modulo-N Counter,  199
	6.16.3.	Johnson Counter,  201
	6.16.4.	Gray Counter,  202
	6.17.	Modeling a Generic Adder,  204
	6.18.	Modeling a Generic Comparator,  205
	6.19.	Modeling a Generic Decoder,  207
	6.19.1.	A Simple Decoder,  207
	6.19.2.	Binary Decoder,  208
	6.19.3.	Johnson Decoder,  209
	6.20.	Modeling a Multiplexer,  210
	6.20.1.	A Simple Multiplexer,  210
	6.20.2.	A Generic Multiplexer,  212
	6.21.	Modeling a Generic Parity Generator Circuit,  215
	6.22.	Modeling a Tri-state Gate,  216
	6.23.	A Count Three 1's Model,  217
	6.24.	A Timer Model,  219
	6.25.	A Factorial Model,  220
	6.26.	A Car Controller Model,  223
	6.27.	A UART Model,  225
	6.28.	A Blackjack Model,  236
Appendix A
Synthesizable Constructs	239
Appendix B
An Arithmetic Package	248
Appendix C
A Generic Library	253


Appendix D
IEEE Standard Arithmetic Packages	261
	D.1.	Summary of Packages,  261
	D.2.	Package NUMERIC_BIT,  263
	D.3.	Package NUMERIC_STD,  276
Bibliography	290