Verilog HDL Synthesis: Table Of Contents

Verilog HDL Synthesis: Table Of Contents

Contents	v
Foreword	xi
Preface	xiii
Chapter 1
Basics	19
	1.1.	What is Synthesis?,  19
	1.2.	Synthesis in a Design Process,  21
	1.3.	Logic Value System,  23
	1.4.	Bit-widths,  24
	1.4.1.	Data Types,  24
	Net Data Type,  24
	1.4.2.	Register Data Type,  26
	1.4.3.	Constants,  27
	1.4.4.	Parameters,  27
	1.5.	Value Holders for Hardware Modeling,  27
Chapter 2
Verilog Constructs to Gates	31
	2.1.	Continuous Assignment Statement,  32
	2.2.	Procedural Assignment Statement,  32
	2.2.1.	Blocking Procedural Assignment,  33
	2.2.2.	Non-blocking Procedural Assignment,  33
	2.2.3.	Target of Assignment,  34
	2.2.4.	Assignment Restrictions,  35
	2.3.	Logical Operators,  36
	2.4.	Arithmetic Operators,  37
	2.4.1.	Unsigned Arithmetic,  37
	2.4.2.	Signed Arithmetic,  38
	2.4.3.	Modeling a Carry,  39
	2.5.	Relational Operators,  39
	2.6.	Equality Operators,  40
	2.7.	Shift Operators,  41
	2.8.	Vector Operations,  43
	2.9.	Part-selects,  44
	2.10.	Bit-selects,  45
	2.10.1.	Constant Index,  45
	2.10.2.	Non-constant Index in Expression,  46
	2.10.3.	Non-constant Index in Target,  46
	2.11.	Conditional Expression,  47
	2.12.	Always Statement,  48
	2.13.	If Statement,  50
	2.13.1.	Inferring Latches from If Statements,  52
	2.14.	Case Statement,  55
	2.14.1.	Casez Statement,  58
	2.14.2.	Casex Statement,  59
	2.14.3.	Inferring Latches from Case Statements,  61
	2.14.4.	Full Case,  62
	2.14.5.	Parallel Case,  64
	2.14.6.	Non-constant as Case Item,  67
	2.15.	More on Latch Inferencing,  68
	Locally Declared Register,  69
	Register Defined Before Use,  70
	Use Before Definition,  71
	2.15.1.	Latch with Asynchronous Preset and Clear,  72
	2.16.	Loop Statement,  73
	2.17.	Modeling Flip-flops,  75
	2.17.1.	Multiple Clocks,  80
	2.17.2.	Multi-phase Clocks,  81
	2.17.3.	With Asynchronous Preset and Clear,  82
	2.17.4.	With Synchronous Preset and Clear,  85
	2.18.	More on Blocking vs Non-blocking Assignments,  87
	2.19.	Functions,  91
	2.20.	Tasks,  92
	2.21.	Using Values x and z,  95
	2.21.1.	The Value x,  95
	2.21.2.	The Value z,  96
	2.22.	Gate Level Modeling,  99
	2.23.	Module Instantiation Statement,  100
	2.23.1.	Using Predefined Blocks,  101
	Instantiating User-built Multipliers,  101
	Instantiating User-specific Flip-flops,  102
	2.24.	Parameterized Designs,  104
Chapter 3
Modeling Examples	107
	3.1.	Modeling a Wire,  108
	3.2.	Modeling Combinational Logic,  110
	3.3.	Modeling Sequential Logic,  111
	3.4.	Modeling a Memory,  111
	3.5.	Writing Boolean Equations,  113
	3.6.	Modeling a Finite State Machine,  114
	3.6.1.	Moore FSM,  114
	3.6.2.	Mealy FSM,  116
	3.6.3.	Encoding States,  119
	Using Integers,  119
	Using Parameter Declarations,  119
	3.7.	Modeling an Universal Shift Register,  120
	3.8.	Modeling an ALU,  122
	3.8.1.	A Parameterized ALU,  122
	3.8.2.	A Simple ALU,  124
	3.9.	Modeling a Counter,  125
	3.9.1.	Ripple Counter,  125
	3.9.2.	Modulo-N Counter,  126
	3.9.3.	Johnson Counter,  127
	3.9.4.	Gray Counter,  128
	3.10.	Modeling a Parameterized Adder,  129
	3.11.	Modeling a Parameterized Comparator,  131
	3.12.	Modeling a Parameterized Decoder,  132
	3.12.1.	A Simple Decoder,  132
	3.12.2.	Binary Decoder,  133
	3.12.3.	Johnson Decoder,  134
	3.13.	Modeling a Multiplexer,  135
	3.13.1.	A Simple Multiplexer,  135
	3.13.2.	A Parameterized Multiplexer,  136
	3.14.	Modeling a Parameterized Parity Generator,  137
	3.15.	Modeling a Three-state Gate,  138
	3.16.	A Count Three 1's Model,  139
	3.17.	A Factorial Model,  141
	3.18.	A UART model,  142
	3.19.	A Blackjack Model,  148
Chapter 4
Model Optimizations	151
	4.1.	Resource Allocation,  152
	4.2.	Common Subexpressions,  155
	4.3.	Moving Code,  156
	4.4.	Common Factoring,  157
	4.5.	Commutativity and Associativity,  157
	4.6.	Other Optimizations,  158
	4.7.	Flip-flop and Latch Optimizations,  159
	4.7.1.	Avoiding Flip-flops,  159
	4.7.2.	Avoiding Latches,  160
	4.8.	Design Size,  161
	Small Designs Synthesize Faster,  161
	Hierarchy,  162
	Macros as Structure,  162
	4.9.	Using Parenthesis,  162
Chapter 5
Verification	165
	5.1.	A Test Bench,  166
	5.2.	Delays in Assignment Statements,  168
	5.3.	Unconnected Ports,  169
	5.4.	Missing Latches,  170
	5.5.	More on Delays,  172
	5.6.	Event List,  173
	5.7.	Synthesis Directives,  175
	5.8.	Comparing with Non-logical Values,  176
Appendix A
Synthesizable Constructs	179
Appendix B
A Generic Library	187
Bibliography	197
Index	199