A Foreword on Verilog Synthesis

The topic of Verilog HDL synthesis has been in existence since 1988, however good textbooks on the topic have not covered basic concepts until now. This practical primer on Verilog HDL synthesis provides a comprehensive and practical description for this new technology. It takes the mystery out of HDL synthesis, by providing an easy to understand Verilog language semantic with respect to synthesis technology. Bhasker is an expert on synthesis: he has worked in synthesis for more than 14 years. He is currently, using his expertise in leading the efforts as the chair of IEEE working group for developing a Verilog RTL synthesis standard (PAR 1364.1) that is based on the OVI RTL synthesis subset 1.0 released in April 1998. Bhasker, is one of the architects for the OVI standard on RTL synthesis standard.

"Verilog HDL Synthesis, A Practical Primer" by J. Bhasker provides students and practicing logic designers with immediate access to an well-organized information about Verilog HDL synthesis. It is easy to read and provides a very large number of examples of synthesizable Verilog models. The reader is led systematically from Verilog language constructs, their meaning in synthesis, how synthesis design technology transforms such constructs into gates, and their impact on design verification. The book is rich in Verilog model examples and their gate equivalence. The examples are simple and they show the different styles of logic modeling such as combinational logic, sequential logic, and register and latched based design, finite state machines, arithmetic units and others. The book is not just unique in covering HDL synthesis for beginners, but also goes into advanced topics such as how to get optimized logic from a synthesis model. Resource sharing and allocation is one of the topics covered under model optimization. Another unique topic is design verification. The book goes into the principles of synthesis model writing to ensure predictable and verifiable results. Although, the chapter is intended for simulation, however, the same concepts can be applied for formal verification.

This book is the first comprehensive treatment for Verilog HDL synthesis. Bhasker has taught Verilog and Verilog synthesis at Lucent for more than 3 years. The book shows the knowledge that Bhasker has accumulated during his 14 years on synthesis. Although this book is targeted for beginners, expert users can benefit from the basic principles as well as advanced modeling topics in synthesis. Definitely, intellectual property (IP) developers should follow the modeling style recommended in this book.

Vassilios C. Gerousis
Senior Staff Technologist, Motorola, Phoenix, Arizona
Chairman, Technical Coordinating Committee (TCC), Open Verilog International